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19-3870; Rev 3; 12/08
Low-Voltage, Quad-/Hex-/Octal-Voltage P Supervisors
General Description
The MAX16000-MAX16007 are low-voltage, quad-/hex-/ octal-voltage P supervisors in small thin QFN and TSSOP packages. These devices provide supervisory functions for complex multivoltage systems. The MAX16000/ MAX16001/MAX16002 monitor four voltages, the MAX16003/MAX16004/MAX16005 monitor six voltages, and the MAX16006/MAX16007 monitor eight voltages. The MAX16000/MAX16001/MAX16003/MAX16004/ MAX16006 offer independent outputs for each monitored voltage. The MAX16001/MAX16002/MAX16004- MAX16007 offer a reset output that asserts whenever any of the monitored voltages fall below their respective thresholds or the manual reset input is asserted. The reset output remains asserted for the reset timeout after all voltages are above their respective thresholds and the manual reset input is deasserted. The minimum reset timeout is internally set to 140ms or can be adjusted with an external capacitor. All open-drain outputs have internal 30A pullups that eliminate the need for external pullup resistors. However, each output can be driven with an external voltage up to 5.5V. Other features offered include a manual reset input, a tolerance pin for selecting 5% or 10% input thresholds, and a margin enable function for deasserting the outputs during margin testing. The MAX16001/MAX16002/MAX16004-MAX16007 offer a watchdog timer that asserts RESET or an independent watchdog output (MAX16005) when the watchdog timeout period (1.6s typ) is exceeded. The watchdog timer can be disabled by floating the input. These devices are offered in 12-, 16-, 20-, and 24-lead thin QFN and 16-lead TSSOP packages. These are fully specified from -40C to +125C.
Features
o Fixed Thresholds for 5V, 3.3V, 3V, 2.5V, 1.8V, 1.5V, 1.2V, and 0.9V Systems o Adjustable Thresholds Monitor Voltages Down to 0.4V o Open-Drain Outputs with Internal Pullups Reduce the Number of External Components o Fixed 140ms (min) or Capacitor-Adjustable Reset Timeout o Manual Reset, Margin Enable, and Tolerance Select Inputs o Watchdog Timer 1.6s (typ) Timeout Period 54s Startup Delay After Reset (Except MAX16005) o Independent Watchdog Output (MAX16005) o RESET Output Indicates All Voltages Present o Independent Voltage Monitors o Guaranteed Correct Logic State Down to VCC = 1V o Small (4mm x 4mm) Thin QFN Package o TSSOP (5mm x 4.4mm) Package (MAX16005)
MAX16000-MAX16007
Ordering Information
PART MAX16000_TC+ TEMP RANGE -40C to +125C PIN-PACKAGE 12 TQFN-EP*
Note: The "_" is a placeholder for the input voltage threshold. See Table 1. +Denotes lead(Pb)-free/RoHS-compliant package. For tape-and-reel, add a "T" after the "+." Tape-and-reel are offered in 2.5k increments. *EP = Exposed pad. Ordering Information continued at end of data sheet.
Typical Operating Circuit Applications
Storage Equipment Servers Networking/Telecommunication Equipment Multivoltage ASICs
VCC VIN1 VIN2 VIN3 VIN4 VIN5 VIN6 IN1 IN2 IN3 IN4 IN5 IN6 MR MAX16005 RESET WDI WDO RST I/O NMI P SRT MARGIN
Selector Guide appears at end of data sheet.
GND
TOL
________________________________________________________________ Maxim Integrated Products
1
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Low-Voltage, Quad-/Hex-/Octal-Voltage P Supervisors MAX16000-MAX16007
ABSOLUTE MAXIMUM RATINGS
VCC, OUT_, IN_, RESET, WDO to GND....................-0.3V to +6V TOL, MARGIN, MR, SRT, WDI, to GND ..........-0.3V to VCC + 0.3 Input/Output Current (RESET, MARGIN, SRT, MR, TOL, OUT_, WDO, WDI) ..............................20mA Continuous Power Dissipation (TA = +70C) 12-Pin TQFN (derate 16.9mW/C above +70C) ........1349mW 16-Pin TQFN (derate 16.9mW/C above +70C) ........1349mW 20-Pin TQFN (derate 16.9mW/C above +70C) ........1355mW 24-Pin TQFN (derate 16.9mW/C above +70C) ........1666mW 16-Pin TSSOP (derate 9.4mW/C above +70C) ..........754mW Operating Temperature Range .........................-40C to +125C Junction Temperature .....................................................+150C Storage Temperature Range .............................-65C to +150C Lead Temperature (soldering, 10s) .................................+300C
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(VCC = 2.0V to 5.5V, TA = -40C to +125C, unless otherwise specified. Typical values are at VCC = 3.3V, TA = +25C.) (Note 1)
PARAMETER Operating Voltage Range Supply Current UVLO (Undervoltage Lockout) IN_ (See Table 1) 5V threshold, TOL = GND 5V threshold, TOL = VCC 3.3V threshold, TOL = GND 3.3V threshold, TOL = VCC 3.0V threshold, TOL = GND 3.0V threshold, TOL = VCC 2.5V threshold, TOL = GND Threshold Voltages (IN_ Falling) VTH 2.5V threshold, TOL = VCC 1.8V threshold, TOL = GND 1.8V threshold, TOL = VCC 1.5V threshold, TOL = GND 1.5V threshold, TOL = VCC 1.2V threshold, TOL = GND 1.2V threshold, TOL = VCC 0.9V threshold, TOL = GND 0.9V threshold, TOL = VCC 4.50 4.25 2.970 2.805 2.70 2.55 2.250 2.125 1.62 1.53 1.350 1.275 1.08 1.02 0.810 0.765 4.625 4.375 3.053 2.888 2.775 2.625 2.313 2.188 1.665 1.575 1.388 1.313 1.11 1.05 0.833 0.788 4.75 4.50 3.135 2.970 2.85 2.70 2.375 2.250 1.71 1.62 1.425 1.350 1.14 1.08 0.855 0.810 V SYMBOL VCC ICC VUVLO (Note 2) VCC = 3.3V, OUT_, RESET not asserted (Note 3) VCC = 5V, OUT_, RESET not asserted VCC rising 1.62 CONDITIONS MIN 1.0 45 50 1.8 TYP MAX 5.5 65 70 1.98 V UNITS V A
2
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Low-Voltage, Quad-/Hex-/Octal-Voltage P Supervisors
ELECTRICAL CHARACTERISTICS (continued)
(VCC = 2.0V to 5.5V, TA = -40C to +125C, unless otherwise specified. Typical values are at VCC = 3.3V, TA = +25C.) (Note 1)
PARAMETER Adjustable Threshold (IN_ Falling) IN_ Hysteresis IN_ Input Current RESET SRT = VCC Reset Timeout tRP CSRT = 1500pF (Note 4) CSRT = 100pF CSRT = open SRT Ramp Current SRT Threshold SRT Hysteresis IN_ to Reset Delay RESET Output-Voltage Low tRD VOL IN_ falling VCC = 3.3V, ISINK = 10mA, RESET asserted VCC = 2.5V, ISINK = 6mA, RESET asserted VCC = 1.2V, ISINK = 50A, RESET asserted RESET Output-Voltage High MR Input-Voltage Low MR Input-Voltage High MR Minimum Pulse Width MR Glitch Rejection MR to Reset Delay MR Pullup Resistance OUTPUTS (OUT_ ) OUT_ Output-Voltage Low OUT_ Output-Voltage High IN_ to OUT_ Propagation Delay VOL VOH tD VCC = 3.3V, ISINK = 2mA VCC = 2.5V, ISINK = 1.2mA VCC 2.0V, ISOURCE = 6A (VTH + 100mV) to (VTH - 100mV) 0.8 x VCC 20 0.30 0.30 V V s Pulled up to VCC 12 VOH VIL VIH 0.7 x VCC 1 100 200 20 28 VCC 2.0V, ISOURCE = 6A, RESET deasserted 0.8 x VCC 0.3 x VCC ISRT VSRT = 0V 460 1.173 140 2.43 200 3.09 0.206 50 600 1.235 100 20 0.30 0.30 0.30 V V V s ns ns k V 740 1.293 s nA V mV s 280 3.92 ms SYMBOL VTH VTH_HYS TOL = GND TOL = VCC IN_ rising Fixed thresholds Adjustable thresholds -100 CONDITIONS MIN 0.388 0.366 TYP 0.394 0.372 0.5 3 16 +100 MAX 0.400 0.378 UNITS V % VTH A nA
MAX16000-MAX16007
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Low-Voltage, Quad-/Hex-/Octal-Voltage P Supervisors MAX16000-MAX16007
ELECTRICAL CHARACTERISTICS (continued)
(VCC = 2.0V to 5.5V, TA = -40C to +125C, unless otherwise specified. Typical values are at VCC = 3.3V, TA = +25C). (Note 1)
PARAMETER Reference Short-Circuit Current Reference Output Accuracy Line Regulation Reference Load Regulation Sourcing, 0 IREF 40A WATCHDOG TIMER (MAX16001/MAX16002/MAX16004-MAX16007) WDI Input-Voltage Low WDI Input-Voltage High WDI Pulse Width Watchdog Timeout Period Watchdog Startup Period Watchdog Input Current WDO Output-Voltage Low (MAX16005 Only) WDO Output-Voltage High (MAX16005 Only) DIGITAL LOGIC TOL Input-Voltage Low TOL Input-Voltage High TOL Input Current MARGIN Input-Voltage Low MARGIN Input-Voltage High MARGIN Pullup Resistance MARGIN Delay Time tMD VIL VIH Pulled up to VCC Rising or falling (Note 6) 0.7 x VCC 12 20 50 28 VIL VIH TOL = VCC 0.7 x VCC 100 0.3 x VCC 0.3 x VCC V V nA V V k s VOL VOH tWDI MAX16001/2/4/6/7 VWDI = 0 to VCC (Note 5) VCC = 3.3V, ISINK = 2mA VCC = 2.5V, ISINK = 1.2mA VCC 2.0V, ISOURCE = 6A, WDO deasserted 0.8 x VCC VIL VIH (Note 5) 0.7 x VCC 50 1.12 35 -1 1.6 54 2.40 72 +1 0.30 0.30 0.3 x VCC V V ns s s A V V VREF SYMBOL CONDITIONS Shorted to GND No load 1.200 MIN TYP 0.8 1.235 0.005 10 1.270 MAX UNITS mA V %/V
REFERENCE OUTPUT (MAX16005 Only)
Note 1: Devices are tested at TA = +25C and guaranteed by design for TA = TMIN to TMAX. Note 2: The outputs are guaranteed to be in the correct logic state down to VCC = 1V. Note 3: Measured with WDI, MARGIN, and MR unconnected. Note 4: The minimum and maximum specifications for this parameter are guaranteed by using the worst case of the SRT ramp current and SRT threshold specifications. Note 5: Guaranteed by design and not production tested. Note 6: Amount of time required for logic to lock/unlock outputs from margin testing.
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Low-Voltage, Quad-/Hex-/Octal-Voltage P Supervisors
Typical Operating Characteristics
(VCC = 3.3V, TA = +25C, unless otherwise noted.)
NORMALIZED THRESHOLD vs. SUPPLY VOLTAGE
MAX16000 toc02
MAX16000-MAX16007
SUPPLY CURRENT vs. SUPPLY VOLTAGE
MAX16000 toc01
SUPPLY CURRENT vs. TEMPERATURE
60 WDI, MARGIN, AND MR UNCONNECTED 55 SUPPLY CURRENT (A) 50 45 40 VCC = 2.5V 35 30 VCC = 3.3V VCC = 5V 1.010 1.008 NORMALIZED THRESHOLD 1.005 1.003 1.000 0.998 0.995 0.993 0.990 -40 -25 -10 5 20 35 50 65 80 95 110 125 TEMPERATURE (C) 1.5 2.0
WDI, MARGIN, AND MR UNCONNECTED 55 SUPPLY CURRENT (A) 50 45 40 35 30 1.5 2.0 2.5 3.0 3.5 4.0 4.5 SUPPLY VOLTAGE (V) 5.0
5.5
2.5 3.0 3.5 4.0 4.5 SUPPLY VOLTAGE (V)
5.0
5.5
NORMALIZED THRESHOLD vs. TEMPERATURE
MAX16000 toc04
OUTPUT VOLTAGE vs. SINK CURRENT
100
MAX16000 toc05
OUTPUT VOLTAGE vs. SOURCE CURRENT
MAX16000 toc06
1.001 1.000 NORMALIZED THRESHOLD 0.999 0.998 0.997
1000
800 VCC - VOUT_ (mV)
75 VOUT_ (mV)
600
50
400
25 0.996 OUT_ LOW 0.995 -40 -25 -10 5 20 35 50 65 80 95 110 125 TEMPERATURE (C) 0 0 1 2 3 4 5 6 SINK CURRENT (mA) 7 8
200 OUT_ HIGH 0 0 5 10 15 20 SOURCE CURRENT (A) 25 30
MAXIMUM TRANSIENT DURATION vs. INPUT OVERDRIVE
MAXIMUM TRANSIENT DURATION (s) OUTPUT GOES LOW ABOVE THIS LINE
MAX16000 toc07
RESET TIMEOUT PERIOD vs. TEMPERATURE
197 RESET TIMEOUT PERIOD (ms) 196 195 194 193 192 191 190
MAX16000 toc08
RESET TIMEOUT DELAY
MAX16000 toc09
600 500 400 300 200 100 0 1 10 100
198
MAX16000 toc03
60
IN1 5V/div
OUT1 2V/div RESET 2V/div SRT = VCC -40 -25 -10 5 20 35 50 65 80 95 110 125 TEMPERATURE (C) 40ms/div
1000
INPUT OVERDRIVE (mV)
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Low-Voltage, Quad-/Hex-/Octal-Voltage P Supervisors MAX16000-MAX16007
Typical Operating Characteristics (continued)
(VCC = 3.3V, TA = +25C, unless otherwise noted.)
RESET TIMEOUT PERIOD vs. CSRT
MAX16000 toc10
WATCHDOG TIMEOUT PERIOD vs. TEMPERATURE
1.59 WATCHDOG TIMEOUT PERIOD (s) 1.58 1.57 1.56 1.55 1.54 1.53 1.52 1.51
MAX16000 toc11
MARGIN ENABLE FUNCTION
MAX16000 toc12
1000
1.60
100
MARGIN 2V/div
tRP (ms)
10
1
OUT_ 2V/div
0.1 0.01 0.01 0.1 1 10 100 1000 CSRT (nF)
OUT_ AND RESET ARE BELOW RESPECTIVE THRESHOLDS -40 -25 -10 5 20 35 50 65 80 95 110 125 TEMPERATURE (C) 100s/div
RESET 2V/div
1.50
MARGIN DISABLE FUNCTION
MAX16000 toc13
REFERENCE VOLTAGE vs. SOURCE CURRENT
MAX16005 MARGIN 2V/div 1.255 1.250 1.245 OUT_ 2V/div RESET 2V/div VREF (V) 1.240 1.235 1.230 1.225 1.220 0 100 200 300 400 500 SOURCE CURRENT (A) 600
MAX16000 toc14 MAX16000 toc16
1.260
OUT_ AND RESET ARE BELOW RESPECTIVE THRESHOLDS
100s/div
REFERENCE VOLTAGE vs. SUPPLY VOLTAGE
MAX16000 toc15
REFERENCE VOLTAGE vs. TEMPERATURE
1.28 MAX16005 1.27 REFERENCE VOLTAGE (V) 1.26 1.25 1.24 1.23 1.22 1.21 1.20
1.260 MAX16005 1.255 REFERENCE VOLTAGE (V) 1.250 1.245 1.240 1.235 1.230 1.225 1.220 1.5 2.0 2.5 3.0 3.5 4.0 4.5 SUPPLY VOLTAGE (V) 5.0
5.5
-40 -25 -10 5 20 35 50 65 80 95 110 125 TEMPERATURE (C)
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Low-Voltage, Quad-/Hex-/Octal-Voltage P Supervisors
Pin Description (MAX16000/MAX16001/MAX16002)
PIN MAX16000 MAX16001 MAX16002 NAME FUNCTION
MAX16000-MAX16007
1 2 3 4 5 6 7 8 9 10 11 12
1 2 4 5 6 7 10 11 12 14 15 16
1 2 4 5 -- -- 8 -- -- 10 11 12
IN3 IN4 GND VCC OUT3 OUT4 MARGIN OUT2 OUT1 IN1 IN2 TOL
Monitored Input Voltage 3. See Table 1 for the input voltage threshold. Monitored Input Voltage 4. See Table 1 for the input voltage threshold. Ground Unmonitored Power-Supply Input Output 3. When the voltage at IN3 falls below its threshold, OUT3 goes low and stays low until the voltage at IN3 exceeds its threshold. The open-drain output has a 30A internal pullup to V CC . Output 4. When the voltage at IN4 falls below its threshold, OUT4 goes low and stays low until the voltage at IN4 exceeds its threshold. The open-drain output has a 30A internal pullup to VCC. Active-Low Manual Deassert Input. Pull MARGIN low to deassert all outputs (go into high state), regardless of the voltage at any monitored input. Output 2. When the voltage at IN2 falls below its threshold, OUT2 goes low and stays low until the voltage at IN2 exceeds its threshold. The open-drain output has a 30A internal pullup to VCC. Output 1. When the voltage at IN1 falls below its threshold, OUT1 goes low and stays low until the voltage at IN1 exceeds its threshold. The open-drain output has a 30A internal pullup to VCC. Monitored Input Voltage 1. See Table 1 for the input voltage threshold. Monitored Input Voltage 2. See Table 1 for the input voltage threshold. Threshold Tolerance Input. Connect TOL to GND to select 5% threshold tolerance. Connect TOL to VCC to select 10% threshold tolerance. Watchdog Timer Input. If WDI remains low or high for longer than the watchdog timeout period, RESET is asserted. The timer clears whenever a reset is asserted or a rising or falling edge on WDI is detected. The watchdog timer enters a startup period that allows 54s for the first transition to occur before a reset. Leave WDI unconnected to disable the watchdog timer. The WDI floating-state detector uses a small 400nA current. Therefore, do not connect WDI to anything that will source or sink more than 200nA. Note that the leakage current specification for most three-state drivers exceeds 200nA. Active-Low Manual Reset Input. Pull MR low to assert RESET low. RESET remains low for the reset timeout period after MR is deasserted. MR is pulled up to VCC through a 20k resistor. Set Reset Timeout Input. Connect a capacitor from SRT to GND to set the reset timeout period. The reset timeout period can be calculated as follows: Reset Timeout (s) = 2.06 x 106 () x CSRT (F). For the internal timeout period of 140ms (min), connect SRT to VCC. Active-Low Reset Output. RESET asserts low when any of the monitored voltages falls below its respective threshold or MR is asserted. RESET remains asserted for the reset timeout period after all monitored voltages exceed their respective thresholds and MR is deasserted. This open-drain output has a 30A internal pullup. Exposed Pad. EP is internally connected to GND. Connect EP to the ground plane to provide a low thermal resistance path from the IC junction to the PCB. Do not use as the electrical connection to GND.
--
3
3
WDI
--
8
6
MR
--
9
7
SRT
--
13
9
RESET
--
--
--
EP
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Low-Voltage, Quad-/Hex-/Octal-Voltage P Supervisors MAX16000-MAX16007
Pin Description (MAX16003/MAX16004/MAX16005)
PIN MAX16005 TSSOP MAX16003 MAX16004 MAX16005 TQFN NAME FUNCTION
1 2 3 4 5 6
1 2 3 5 6 7
3 4 5 7 8 --
1 2 3 5 6 --
IN4 IN5 IN6 GND VCC OUT4
Monitored Input Voltage 4. See Table 1 for the input voltage threshold. Monitored Input Voltage 5. See Table 1 for the input voltage threshold. Monitored Input Voltage 6. See Table 1 for the input voltage threshold. Ground Unmonitored Power-Supply Input Output 4. When the voltage at IN4 falls below its threshold, OUT4 goes low and stays low until the voltage at IN4 exceeds its threshold. The open-drain output has a 30A internal pullup to VCC. Output 5. When the voltage at IN5 falls below its threshold, OUT5 goes low and stays low until the voltage at IN5 exceeds its threshold. The open-drain output has a 30A internal pullup to VCC. Output 6. When the voltage at IN6 falls below its threshold, OUT6 goes low and stays low until the voltage at IN6 exceeds its threshold. The open-drain output has a 30A internal pullup to VCC. Manual Deassert Input. Pull MARGIN low to deassert all outputs (go into high state), regardless of the voltage at any monitored input. Output 3. When the voltage at IN3 falls below its threshold, OUT3 goes low and stays low until the voltage at IN3 exceeds its threshold. The open-drain output has a 30A internal pullup to VCC. Output 2. When the voltage at IN2 falls below its threshold, OUT2 goes low and stays low until the voltage at IN2 exceeds its threshold. The open-drain output has a 30A internal pullup to VCC. Output 1. When the voltage at IN1 falls below its threshold, OUT1 goes low and stays low until the voltage at IN1 exceeds its threshold. The open-drain output has a 30A internal pullup to VCC. Monitored Input Voltage 1. See Table 1 for the input voltage threshold. Monitored Input Voltage 2. See Table 1 for the input voltage threshold. Monitored Input Voltage 3. See Table 1 for the input voltage threshold.
7
8
--
--
OUT5
8
9
--
--
OUT6
9
12
13
11
MARGIN
10
13
--
--
OUT3
11
14
--
--
OUT2
12 13 14 15
15 17 18 19
-- 15 16 1
-- 13 14 15
OUT1 IN1 IN2 IN3
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Low-Voltage, Quad-/Hex-/Octal-Voltage P Supervisors
Pin Description (MAX16003/MAX16004/MAX16005) (continued)
PIN MAX16005 TSSOP MAX16003 MAX16004 MAX16005 TQFN NAME FUNCTION
MAX16000-MAX16007
16
20
2
16
TOL
Threshold Tolerance Input. Connect TOL to GND to select 5% threshold tolerance. Connect TOL to VCC to select 10% threshold tolerance. Watchdog Timer Input. MAX16004: If WDI remains low or high for longer than the watchdog timeout period, RESET is asserted and the timer is cleared. The timer also clears whenever a reset is asserted or a rising or falling edge on WDI is detected. The watchdog timer enters a startup period that allows 54s for the first transition to occur before a reset. Leave WDI unconnected to disable the watchdog timer. MAX16005: If WDI remains low or high for longer than the watchdog timeout period, WDO is asserted. The timer clears whenever a rising or falling edge on WDI is detected. Leave WDI unconnected to disable the watchdog timer. The MAX16005 does not have a startup period. MAX16004/MAX16005: The WDI floating-state detector uses a small 100nA current. Therefore, do not connect WDI to anything that will source or sink more than 50nA. Note that the leakage current specification for most three-state drivers exceeds 50nA. Active-Low Manual Reset Input. Pull MR low to assert RESET low. RESET remains low for the reset timeout period after MR is deasserted. MR is pulled up to VCC through a 20k resistor. Set Reset Timeout Input. Connect a capacitor from SRT to GND to set the reset timeout period. The reset timeout period can be calculated as follows: Reset Timeout (s) = 2.06 x 106 () x CSRT (F). For the internal timeout period of 140ms (min), connect SRT to VCC. Active-Low Reset Output. RESET asserts low when any of the monitored voltages falls below its respective threshold or MR is asserted. RESET remains asserted for the reset timeout period after all monitored voltages exceed their respective thresholds and MR is deasserted. This open-drain output has a 30A internal pullup. Reference Output. The reference output voltage of 1.23V can source up to 40A. Active-Low Watchdog Output. WDO asserts and stays low whenever any of the IN_ inputs fall below their respective thresholds. WDO deasserts without a timeout delay when all the IN_ inputs rise above their thresholds. When all the IN_ inputs rise above their thresholds, WDO asserts low whenever the watchdog timer times out. WDO deasserts after a valid WDI transition or if MR is pulled low. The watchdog timer begins counting after the reset timeout period once MR goes high. Pull MARGIN low to deassert WDO. Exposed Pad. EP is internally connected to GND. Connect EP to the ground plane to provide a low thermal resistance path from the IC junction to the PCB. Do not use as the electrical connection to GND.
--
4
6
4
WDI
--
10
11
9
MR
--
11
12
10
SRT
--
16
14
12
RESET
--
--
9
7
REF
--
--
10
8
WDO
--
--
--
--
EP
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Low-Voltage, Quad-/Hex-/Octal-Voltage P Supervisors MAX16000-MAX16007
Pin Description (MAX16006/MAX16007)
PIN MAX16006 MAX16007 NAME FUNCTION
1 2 3 4
1 2 3 4
IN5 IN6 IN7 IN8
Monitored Input Voltage 5. See Table 1 for the input voltage threshold. Monitored Input Voltage 6. See Table 1 for the input voltage threshold. Monitored Input Voltage 7. See Table 1 for the input voltage threshold. Monitored Input Voltage 8. See Table 1 for the input voltage threshold. Watchdog Timer Input. If WDI remains low or high for longer than the watchdog timeout period, RESET is asserted and the timer is cleared. The timer also clears whenever a reset is asserted or a rising or falling edge on WDI is detected. The watchdog timer enters a startup period that allows 54s for the first transition to occur before a reset. Leave WDI unconnected to disable the watchdog timer. The WDI floating-state detector uses a small 400nA current. Therefore, do not connect WDI to anything that will source or sink more than 200nA. Note that the leakage current specification for most three-state drivers exceeds 200nA. Ground Unmonitored Power-Supply Input Output 5. When the voltage at IN5 falls below its threshold, OUT5 goes low and stays low until the voltage at IN5 exceeds its threshold. The open-drain output has a 30A internal pullup to VCC. Output 6. When the voltage at IN6 falls below its threshold, OUT6 goes low and stays low until the voltage at IN6 exceeds its threshold. The open-drain output has a 30A internal pullup to VCC. Output 7. When the voltage at IN7 falls below its threshold, OUT7 goes low and stays low until the voltage at IN7 exceeds its threshold. The open-drain output has a 30A internal pullup to VCC. Output 8. When the voltage at IN8 falls below its threshold, OUT8 goes low and stays low until the voltage at IN8 exceeds its threshold. The open-drain output has a 30A internal pullup to VCC. Active-Low Manual Reset Input. Pull MR low to assert RESET low. RESET remains low for the reset timeout period after MR is deasserted. MR is pulled up to VCC through a 20k resistor. Set Reset Timeout Input. Connect a capacitor from SRT to GND to set the reset timeout period. The reset timeout period can be calculated as follows: Reset Timeout (s) = 2.06 x 106 () x CSRT (F). For the internal timeout period of 140ms (min), connect SRT to VCC.
5
5
WDI
6 7 8 9 10 11 12
6 7 -- -- -- -- 10
GND VCC OUT5 OUT6 OUT7 OUT8 MR
13
11
SRT
10
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Low-Voltage, Quad-/Hex-/Octal-Voltage P Supervisors MAX16000-MAX16007
Pin Description (MAX16006/MAX16007) (continued)
PIN MAX16006 MAX16007 NAME FUNCTION
14 15 16 17 18
12 -- -- -- --
MARGIN OUT4 OUT3 OUT2 OUT1
Margin Disable Input. Pull MARGIN low to deassert all outputs (go into high state), regardless of the voltage at any monitored input. Output 4. When the voltage at IN4 falls below its threshold, OUT4 goes low and stays low until the voltage at IN4 exceeds its threshold. The open-drain output has a 30A internal pullup to VCC. Output 3. When the voltage at IN3 falls below its threshold, OUT3 goes low and stays low until the voltage at IN3 exceeds its threshold. The open-drain output has a 30A internal pullup to VCC. Output 2. When the voltage at IN2 falls below its threshold, OUT2 goes low and stays low until the voltage at IN2 exceeds its threshold. The open-drain output has a 30A internal pullup to VCC. Output 1. When the voltage at IN1 falls below its threshold, OUT1 goes low and stays low until the voltage at IN1 exceeds its threshold. The open-drain output has a 30A internal pullup to VCC. Active-Low Reset Output. RESET asserts low when any of the monitored voltages falls below its respective threshold or MR is asserted. RESET remains asserted for the reset timeout period after all monitored voltages exceed their respective thresholds and MR is deasserted. This open-drain output has a 30A internal pullup. Monitored Input Voltage 1. See Table 1 for the input voltage threshold. Monitored Input Voltage 2. See Table 1 for the input voltage threshold. Monitored Input Voltage 3. See Table 1 for the input voltage threshold. Monitored Input Voltage 4. See Table 1 for the input voltage threshold. Threshold Tolerance Input. Connect TOL to GND to select 5% threshold tolerance. Connect TOL to VCC to select 10% threshold tolerance. Not Internally Connected Exposed Pad. EP is internally connected to GND. Connect EP to the ground plane to provide a low thermal resistance path from the IC junction to the PCB. Do not use as the electrical connection to GND.
19
15
RESET
20 21 22 23 24 -- --
16 17 18 19 20 8, 9, 13, 14 --
IN1 IN2 IN3 IN4 TOL N.C. EP
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Low-Voltage, Quad-/Hex-/Octal-Voltage P Supervisors MAX16000-MAX16007
Table 1. Input-Voltage-Threshold Selector
PART MAX16000A MAX16000B MAX16000C MAX16000D MAX16000E MAX16001A MAX16001B MAX16001C MAX16001D MAX16001E MAX16002A MAX16002B MAX16002C MAX16002D MAX16002E MAX16003A MAX16003B MAX16003C MAX16003D MAX16003E MAX16004A MAX16004B MAX16004C MAX16004D MAX16004E MAX16005A MAX16005B MAX16005C MAX16005D MAX16005E MAX16006A MAX16006B MAX16006C MAX16006D MAX16006E MAX16006F MAX16007A MAX16007B MAX16007C MAX16007D IN1 3.3 3.3 ADJ 3.3 ADJ 3.3 3.3 ADJ 3.3 ADJ 3.3 3.3 ADJ 3.3 ADJ 3.3 3.3 3.3 ADJ ADJ 3.3 3.3 3.3 ADJ ADJ 3.3 3.3 3.3 ADJ ADJ 3.3 3.3 3.3 ADJ ADJ 5.0 3.3 3.3 3.3 ADJ IN2 2.5 ADJ 2.5 2.5 ADJ 2.5 ADJ 2.5 2.5 ADJ 2.5 ADJ 2.5 2.5 ADJ 2.5 ADJ 2.5 2.5 ADJ 2.5 ADJ 2.5 2.5 ADJ 2.5 ADJ 2.5 2.5 ADJ 2.5 ADJ 2.5 2.5 ADJ 3.3 2.5 ADJ 2.5 2.5 IN3 ADJ ADJ ADJ ADJ ADJ ADJ ADJ ADJ ADJ ADJ ADJ ADJ ADJ ADJ ADJ ADJ ADJ ADJ ADJ ADJ ADJ ADJ ADJ ADJ ADJ ADJ ADJ ADJ ADJ ADJ ADJ ADJ ADJ ADJ ADJ 3.0 ADJ ADJ ADJ ADJ IN4 1.8 1.8 1.8 ADJ ADJ 1.8 1.8 1.8 ADJ ADJ 1.8 1.8 1.8 ADJ ADJ 1.8 1.8 ADJ 1.8 ADJ 1.8 1.8 ADJ 1.8 ADJ 1.8 1.8 ADJ 1.8 ADJ 1.8 1.8 ADJ 1.8 ADJ 2.5 1.8 1.8 ADJ 1.8 IN5 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- ADJ ADJ ADJ ADJ ADJ ADJ ADJ ADJ ADJ ADJ ADJ ADJ ADJ ADJ ADJ ADJ ADJ ADJ ADJ ADJ 1.8 ADJ ADJ ADJ ADJ IN6 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- ADJ ADJ ADJ ADJ ADJ ADJ ADJ ADJ ADJ ADJ ADJ ADJ ADJ ADJ ADJ ADJ ADJ ADJ ADJ ADJ 1.5 ADJ ADJ ADJ ADJ IN7 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- ADJ ADJ ADJ ADJ ADJ 1.2 ADJ ADJ ADJ ADJ IN8 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- ADJ ADJ ADJ ADJ ADJ 0.9 ADJ ADJ ADJ ADJ ADJ
MAX16007E ADJ ADJ ADJ ADJ ADJ ADJ ADJ Note: Other fixed thresholds may be available. Contact factory for availability. 12 ______________________________________________________________________________________
Low-Voltage, Quad-/Hex-/Octal-Voltage P Supervisors MAX16000-MAX16007
Functional Diagrams
VCC VCC RESET CIRCUIT IN1
OUT1
IN2 OUT2
OUTPUT DRIVER IN3 OUT3
EN IN4 OUT4
VCC TOL REFERENCE
VCC MAX16000 UNDERVOLTAGE LOCKOUT VCC
MARGIN
Figure 1. MAX16000D Functional Diagram
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Low-Voltage, Quad-/Hex-/Octal-Voltage P Supervisors MAX16000-MAX16007
Functional Diagrams (continued)
WDI MR SRT VCC VCC WATCHDOG TIMER CIRCUIT TIMING RESET CIRCUIT IN1 RESET
(OUT1)
IN2 (OUT2)
OUTPUT DRIVER IN3 (OUT3)
EN IN4 (OUT4)
VCC TOL REFERENCE
VCC UNDERVOLTAGE LOCKOUT VCC MAX16001/ MAX16002
( ) MAX16001 ONLY
MARGIN
Figure 2. MAX16001D/MAX16002D Functional Diagram
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Low-Voltage, Quad-/Hex-/Octal-Voltage P Supervisors MAX16000-MAX16007
Functional Diagrams (continued)
(WDI) (MR) (SRT) VCC VCC WATCHDOG TIMER CIRCUIT TIMING RESET CIRCUIT IN1 (RESET)
OUT1 IN2
OUT2 IN3
OUT3 OUTPUT DRIVER IN4
OUT4
IN5
OUT5
IN6
EN
OUT6
VCC TOL REFERENCE
VCC UNDERVOLTAGE LOCKOUT VCC MAX16003/ MAX16004
MARGIN ( ) MAX16004 ONLY
Figure 3. MAX16003C/MAX16004C Functional Diagram
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Low-Voltage, Quad-/Hex-/Octal-Voltage P Supervisors MAX16000-MAX16007
Functional Diagrams (continued)
WDO WDI MR SRT VCC VCC WATCHDOG TIMER CIRCUIT TIMING RESET CIRCUIT IN1 RESET
IN2
IN3
OUTPUT DRIVER IN4
IN5
IN6
EN
VCC TOL REFERENCE
VCC UNDERVOLTAGE LOCKOUT VCC MAX16005
REF
MARGIN
Figure 4. MAX16005C Functional Diagram
16
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Low-Voltage, Quad-/Hex-/Octal-Voltage P Supervisors MAX16000-MAX16007
Functional Diagrams (continued)
WDI MR SRT VCC VCC WATCHDOG TIMER CIRCUIT TIMING RESET CIRCUIT IN1 RESET
(OUT1) IN2
(OUT2) IN3
(OUT3) OUTPUT DRIVER IN4
(OUT4)
IN5
(OUT5)
IN6 (OUT6)
IN7 (OUT7)
IN8
EN
OUT8
VCC TOL REFERENCE
VCC UNDERVOLTAGE LOCKOUT VCC MAX16006/ MAX16007
( ) MAX16006 ONLY
MARGIN
Figure 5. MAX16006C/MAX16007C Functional Diagram
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Low-Voltage, Quad-/Hex-/Octal-Voltage P Supervisors MAX16000-MAX16007
Detailed Description
The MAX16000-MAX16007 are low-voltage, quad-/hex-/ octal-voltage P supervisors in small thin QFN and TSSOP packages. These devices provide supervisory functions for complex multivoltage systems. The MAX16000/ MAX16001/MAX16002 monitor four voltages, the MAX16003/MAX16004/MAX16005 monitor six voltages, and the MAX16006/MAX16007 monitor eight voltages. The MAX16000/MAX16001/MAX16003/MAX16004/ MAX16006 offer independent outputs for each monitored voltage. The MAX16001/MAX16002/MAX16004- MAX16007 offer a reset output that asserts whenever any of the monitored voltages fall below their respective thresholds or the manual reset input is asserted. The reset output remains asserted for the reset timeout after all voltages are above their respective thresholds and the manual reset input is deasserted. The minimum reset timeout is internally set to 140ms or can be adjusted with an external capacitor. All open-drain outputs have internal 30A pullups that eliminate the need for external pullup resistors. However, each output can be driven with an external voltage up to 5.5V. Other features offered include a manual reset input, a tolerance pin for selecting 5% or 10% input thresholds, and a margin enable function for deasserting the outputs during margin testing. The MAX16001/MAX16002/MAX16004-MAX16007 offer a watchdog timer that asserts RESET or an independent watchdog output (MAX16005) when the watchdog timeout period (1.6s typ) is exceeded. The watchdog timer can be disabled by floating the input.
Window Detection
A window detector circuit uses two auxiliary inputs in the configuration shown in Figure 8. External resistors set the two threshold voltages of the window detector circuit. External logic gates create the OUT signal. The window detection width is the difference between the threshold voltages (Figure 9).
5V VCC V1 V2 V3 V4 IN1 IN2 IN3 IN4 MAX16000 MAX16001 OUT1 OUT2 OUT3 OUT4 GND
Figure 6. Quad Undervoltage Detector with LED Indicators
5V D1
Applications Information
Undervoltage-Detection Circuit
The open-drain outputs of the MAX16000-MAX16007 can be configured to detect an undervoltage condition. Figure 6 shows a configuration where an LED turns on when the comparator output is low, indicating an undervoltage condition. These devices can also be used in applications such as system supervisory monitoring, multivoltage level detection, and VCC bar-graph monitoring (Figure 7).
VIN(5V)
VCC IN1
OUT1
D2
OUT2 IN2 D3 IN3 MAX16000 MAX16001 OUT3 IN4 D4
Tolerance (TOL)
The MAX16000-MAX16007 feature a pin-selectable threshold tolerance. Connect TOL to GND to select 5% threshold tolerance. Connect TOL to VCC to select 10% threshold tolerance.
GND
OUT4
Figure 7. VCC Bar-Graph Monitoring
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Low-Voltage, Quad-/Hex-/Octal-Voltage P Supervisors MAX16000-MAX16007
VTH1 =
(1 + R1) (VTH + VTH_HYS) R2
R1 IN1 R2 IN2 IN3 R3 IN4 R4
VINTH
5V
R1
VCC OUT1 MAX16000 OUT2 MAX16001 OUT3
R2
OUT
INPUT
VTH
OUT4 GND
V R1 = R2( INTH - 1 VTH
)
Figure 10. Setting the Adjustable Input
VTH4 = R3 (1 + R4) VTH
Adjustable Input
Figure 8. Window Detection
OUT1
V TH1
These devices offer several monitor options with adjustable input thresholds (see Table 1). The threshold voltage at each adjustable IN_ input is typically 0.394V (TOL = GND) or 0.372 (TOL = VCC). To monitor a voltage VINTH, connect a resistive-divider network to the circuit as shown in Figure 10. VINTH = VTH ((R1 / R2) + 1) R1 = R2 ((VINTH / VTH) - 1) Large resistors can be used to minimize current through the external resistors. For greater accuracy, use lowervalue resistors.
Unused Inputs
OUT4 V TH4
Connect any unused IN_ inputs to a voltage above its threshold.
OUT_ Outputs (MAX16000/MAX16001/MAX16003/ MAX16004/MAX16006)
OUT V TH
Figure 9. Output Response of Window Detector Circuit
The OUT_ outputs go low when their respective IN_ inputs drop below their specified thresholds. The output is open drain with a 30A internal pullup to VCC. For many applications, no external pullup resistor is required to interface with other logic devices. An external pullup resistor to any voltage from 0 to 5.5V overrides the internal pullup if interfacing to different logic supply voltages. Internal circuitry prevents reverse current flow from the external pullup voltage to VCC (Figure 11).
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19
Low-Voltage, Quad-/Hex-/Octal-Voltage P Supervisors MAX16000-MAX16007
VCC = 3.3V 5V
IN_ VTH_
VTH_
100k VCC VCC
RESET 90% 10% tRD tRP
OUT_
RESET
OUT_
90% 10%
MAX16001/ MAX16002/ MAX16004-MAX16007 GND GND
tD
tD
Figure 11. Interfacing to a Different Logic Supply Voltage
Figure 12. Output Timing Diagram
RESET Output (MAX16001/MAX16002/ MAX16004-MAX16007)
RESET asserts low when any of the monitored voltages fall below their respective thresholds or MR is asserted. RESET remains asserted for the reset timeout period after all monitored voltages exceed their respective thresholds and MR is deasserted (see Figure 12). This open-drain output has a 30A internal pullup. An external pullup resistor to any voltage from 0 to 5.5V overrides the internal pullup if interfacing to different logic supply voltages. Internal circuitry prevents reverse current flow from the external pullup voltage to VCC (Figure 11).
WDO (MAX16005 Only)
WDO asserts and stays low whenever any of the IN_ inputs fall below their respective thresholds. WDO deasserts without a timeout delay when all the IN_ inputs rise above their thresholds. When all the IN_ inputs rise above their thresholds, WDO asserts low whenever the watchdog timer times out. WDO deasserts after a valid WDI transition or if MR is pulled low. The watchdog timer begins counting after the reset timeout period once MR goes high. Pull MARGIN low to deassert WDO regardless of any other condition. The watchdog timer continues to run when MARGIN is low and if a timeout occurs. WDO will assert MR after MARGIN is deasserted. This open-drain output has a 30A internal pullup. An external pullup resistor to any voltage from 0 to 5.5V overrides the internal pullup if interfacing to different logic supply voltages. Internal circuitry prevents reverse current flow from the external pullup voltage to VCC (Figure 11).
20
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Low-Voltage, Quad-/Hex-/Octal-Voltage P Supervisors MAX16000-MAX16007
VTH + VTH_HYST VTH VIN VTH + VTH_HYST
RESET
tRP
tRP
WDO
WDI tFigure 13. WDO Timing Related to VTH and tRP
VTH + VTH_HYST VIN VTH
VTH + VTH_HYST
MARGIN
RESET
tWD INTERNAL RESET SIGNAL tRP
tRP
Figure 14. Margin Output Disable (MARGIN) Affect on RESET within tRP
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Low-Voltage, Quad-/Hex-/Octal-Voltage P Supervisors MAX16000-MAX16007
VTH + VTH_HYST VIN VTH VTH + VTH_HYST
MARGIN
RESET
INTERNAL RESET SIGNAL
tRP
tRP
Figure 15. Margin Output Disable (MARGIN) Affect on RESET Outside tRP
Reset Timeout Capacitor
The reset timeout period can be adjusted to accommodate a variety of P applications from 50s to 1.12s. Adjust the reset timeout period (tRP) by connecting a capacitor (CSRT) between SRT and GND. Calculate the reset timeout capacitor as follows: t (s) x ISRT CSRT (F) = RP VTH _ SRT Connect SRT to VCC for a factory-programmed reset timeout of 140ms (min).
MR to GND to create a manual reset function. External debounce circuitry is not required. If MR is driven from long cables or if the device is used in a noisy environment, connecting a 0.1F capacitor from MR to GND provides additional noise immunity.
Margin Output Disable (MARGIN)
MARGIN allows system-level testing while power supplies are adjusted from their nominal voltages. Drive MARGIN low to force RESET, WDO, and OUT_ high, regardless of the voltage at any monitored input. The state of each output does not change while MARGIN = GND. The watchdog timer continues to run when MARGIN is low, and if a timeout occurs, WDO/RESET will assert tMD after MARGIN is deasserted. The MARGIN input is internally pulled up to VCC. Leave MARGIN unconnected or connect to VCC if unused.
Manual Reset Input (MR) (MAX16001/MAX16002/ MAX16004-MAX16007)
Many P-based products require manual reset capability, allowing the operator, a test technician, or external logic circuitry to initiate a reset. A logic-low on MR asserts RESET low. RESET remains asserted while MR is low, and during the reset timeout period (140ms min) after MR returns high. The MR input has an internal 20k pullup resistor to VCC, so it can be left unconnected if not used. MR can be driven with TTL or CMOS-logic levels, or with open-drain/collector outputs. Connect a normally open momentary switch from
22
Power-Supply Bypassing
The MAX16000-MAX16007 operate from a 2.0V to 5.5V supply. An undervoltage lockout ensures that the outputs are in the correct states when the UVLO is exceeded. In noisy applications, bypass VCC to ground with a 0.1F capacitor as close to the device as possible. The additional capacitor improves transient immunity. For fast-rising VCC transients, additional capacitance may be required
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Low-Voltage, Quad-/Hex-/Octal-Voltage P Supervisors MAX16000-MAX16007
Pin Configurations
MARGIN
OUT1
OUT2
9
8
7
9
8
IN1 10
6
OUT4
SRT 7
TOP VIEW
TOP VIEW
MARGIN
RESET
IN1 10
6
MR
IN2 11
MAX16000
5
OUT3
IN2 11
MAX16002
5
VCC
TOL 12
4 +
VCC
TOL 12
4 +
GND
1 IN3
2 IN4
3 GND
1 IN3
2 IN4
3 WDI 10 OUT3 MARGIN 9
THIN QFN (4mm x 4mm)
THIN QFN (4mm x 4mm)
OUT1
OUT2
OUT1 12
12
11
10
9
11
RESET 13 IN1 14 IN2 15 TOL 16 +
8 7
MR OUT4 OUT3 VCC
OUT2
SRT
TOP VIEW
MARGIN
TOP VIEW
IN1 13 IN2 14 IN3 15 TOL 16 +
8 7
OUT6 OUT5 OUT4 VCC
MAX16001
6 5
MAX16003
6 5
1 IN3
2 IN4
3 WDI
4 GND
1 IN4
2 IN5
3 IN6
4 GND
THIN QFN (4mm x 4mm)
THIN QFN (4mm x 4mm)
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23
Low-Voltage, Quad-/Hex-/Octal-Voltage P Supervisors MAX16000-MAX16007
Pin Configurations (continued)
MARGIN OUT1 OUT2 OUT3 SRT SRT 13 12 11 10 MR OUT8 OUT7 OUT6 OUT5 VCC 9 8 + TOL 24 1 IN4 2 IN5 3 IN6 4 WDI 5 GND 1 IN5 2 IN6 3 IN7 4 IN8 5 WDI 6 GND 16 IN2 15 IN1 14 RESET 13 MARGIN 12 SRT 11 MR 10 WDO 9 REF 7 MARGIN 14
OUT1
OUT2
OUT3 16 +
TOP VIEW
TOP VIEW
15 RESET 16 IN1 17 IN2 18 IN3 19 TOL 20 +
14
13
12
11 RESET 19 10 9 MR IN1 20 OUT6 IN2 21 OUT5 IN3 22 7 6 OUT4 IN4 23 VCC
18
17
15
MAX16004
8
MAX16006
THIN QFN (4mm x 4mm)
MARGIN RESET SRT MR
THIN QFN (4mm x 4mm) TOP VIEW
IN3 1 8 7 WDO REF VCC GND TOL 2 IN4 3
TOP VIEW
12
11
10
9
IN1 13 IN2 14 IN3 15 TOL 16 +
IN5 4 IN6 5 WDI 6
MAX16005
MAX16005
6 5
GND 7 VCC 8 MARGIN
1 IN4
2 IN5
3 IN6
4 N.C. N.C.
THIN QFN (4mm x 4mm)
IN1 16 IN2 17 IN3 18 IN4 19 TOL 20
15
14
13
12
SRT
TOP VIEW
RESET
WDI
TSSOP
11 10 9 MR N.C. N.C. VCC GND
MAX16007
8 7
+
6 2 IN6 3 IN7 4 IN8 5 WDI
1 IN5
THIN QFN (4mm x 4mm)
24
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OUT4
Low-Voltage, Quad-/Hex-/Octal-Voltage P Supervisors
Ordering Information (continued)
PART MAX16001_TE+ MAX16002_TC+ MAX16003_TE+ MAX16004_TP+ MAX16005_TE+ MAX16005_UE+ MAX16006_TG+ MAX16007_TP+ TEMP RANGE -40C to +125C -40C to +125C -40C to +125C -40C to +125C -40C to +125C -40C to +125C -40C to +125C -40C to +125C PIN-PACKAGE 16 TQFN-EP* 12 TQFN-EP* 16 TQFN-EP* 20 TQFN-EP* 16 TQFN-EP* 16 TSSOP 24 TQFN-EP* 20 TQFN-EP*
Chip Information
PROCESS: BiCMOS
MAX16000-MAX16007
Note: The "_" is a placeholder for the input voltage threshold. See Table 1. +Denotes lead(Pb)-free/RoHS-compliant package. For tape-and-reel, add a "T" after the "+." Tape-and-reel are offered in 2.5k increments. *EP = Exposed pad.
Selector Guide
PART MAX16000 MAX16001 MAX16002 MAX16003 MAX16004 MAX16005 MAX16006 MAX16007 MONITORED VOLTAGES 4 4 4 6 6 6 8 8 INDEPENDENT OUTPUTS 4 4 -- 6 6 -- 8 -- RESET -- -- WDI/WDO -- WDI WDI -- WDI WDI/WDO WDI WDI MR -- -- ADJUSTABLE RESET TIMEOUT -- --
Package Information
For the latest package outline information and land patterns, go to www.maxim-ic.com/packages. PACKAGE TYPE 12 TQFN 16 TSSOP 16 TQFN 20 TQFN 24 TQFN PACKAGE CODE T1244-4 U16-2 T1644-4 T2044-3 T2444-4 DOCUMENT NO. 21-0139 21-0108 21-0139 21-0139 21-0139
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25
Low-Voltage, Quad-/Hex-/Octal-Voltage P Supervisors MAX16000-MAX16007
Revision History
REVISION NUMBER 0 1 2 3 REVISION DATE 12/05 1/06 7/06 12/08 Initial release Released MAX16003 and MAX16004. Released MAX16005. Updated Pin Description and Detailed Description. Added the MAX16005 TSSOP package. Modified the Detailed Description, and added Figures 13, 14, and 15. DESCRIPTION PAGES CHANGED -- 20, 21 1, 4, 7, 9, 10, 20, 21 1, 2, 7, 8, 9, 10, 20-26
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
26 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 (c) 2008 Maxim Integrated Products is a registered trademark of Maxim Integrated Products. Inc.

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